Electronic devices are pervasive in many applications from computers to automobiles. Many of the digital circuits in electronic devices operate with a clock signal. The clocking needs of particular circuits inside a system may be different to each other for a variety of reasons. For example, a slower clock may be desired for a particular sub-block to reduce power consumption. A common technique typically used to provide appropriate clocking to each circuit in a system is to generate sub-clocks from a first clock, where the sub-clocks may have a different clocking frequency than the first clock.
A common technique used to generate a slow clock from a fast clock is by using a prescaler circuit. A prescaler circuit, also known as a clock divider, is an electronic circuit configured to receive an input clock and generate an output clock with a lower frequency than the input clock. For example, the output clock may have a frequency that is four times slower than the frequency of the input clock. Such divided clock may serve as an input for other sub-blocks, such as counters, computational elements and other digital circuits, phase locked loop (PLL), and other circuits known in the art.
A programmable clock divider is a clock divider that may divide an input clock by a programmable integer number. The integer number may be programmed dynamically by using registers, digital signals, digital communications or any other way known in the art.